#ifndef _ALGA_AMD_DCE4_DCE4_H
#define _ALGA_AMD_DCE4_DCE4_H
/*
  author Sylvain Bertrand <digital.ragnarok@gmail.com>
  Protected by GNU Affero GPL v3 with some exceptions.
  See README at root of alga tree.
*/

#define CRTCS_N_MAX 6
#define HPDS_N 6

#ifdef __KERNEL__
#define DCE4_ERR 1000

struct db_fb {
	u64 primary;
	u64 secondary;
	enum alga_pixel_fmt pixel_fmt;

	struct alga_timing timing;
	unsigned pitch;
};

/* major programming functions: do lock dce state */
struct dce4;
#include <alga/amd/dce4/dce4_dev.h>
struct dce4 *dce4_alloc(struct dce4_dev *ddev);
int dce4_init(struct dce4 *dce, u32 dmif_addr_cfg);
void dce4_shutdown(struct dce4 *dce);
int dce4_sink_mode_set(struct dce4 *dce, unsigned i, struct db_fb *db_fb);
int dce4_dps_info(struct dce4 *dce, unsigned *used, unsigned *connected,
		enum alga_pixel_fmt (*fmts)[CRTCS_N_MAX][ALGA_PIXEL_FMTS_MAX],
		struct alga_timing (*ts)[CRTCS_N_MAX][ALGA_TIMINGS_MAX]);
int dce4_dp_dpm(struct dce4 *dce, unsigned i);
/* irq thread */
int dce4_irqs_thd(struct dce4 *dce);

/* hard interrupt context: ack and tag hpd/pf events */
void dce4_hpd_irq(struct dce4 *dce, unsigned hpd);
void dce4_pf_irq(struct dce4 *dce, unsigned i);

/* direct hardware access */
void dce4_vga_off(struct dce4 *dce);
void dce4_irqs_ack(struct dce4 *dce);
void dce4_intrs_reset(struct dce4 *dce);
void dce4_hpds_intr_ena(struct dce4 *dce);
int dce4_pf(struct dce4 *dce, unsigned i, unsigned *vblanks_n);

/* direct atombios access */
int dce4_mem_req(struct dce4 *dce, bool ena);
#endif
#endif
